The present invention relates to channels for data processing systems providing data transfers between the data processing systems and connected data links, and more particularly relates to a synchronizing circuit for synchronizing data transfers from a data processing channel onto a data link.
The transfer of data over a data link by a data processing system may be either in a start-stop mode in which the data link is operated in an asynchronous manner with the data message over the link being proceeded by a special start character and ended by a special stop character, or in a synchronous mode wherein both the sender and the receiver are operated in synchronism with one another with a message being proceeded by a special synchronizing bit or character pattern. In the data link of the present invention, both the sender and the receiver are kept in continuous synchronous operation by always transmitting intelligible data characters over the link. When message frames are not being transmitted, idle characters are transmitted to keep the data link in synchronism. Since the sender and the receiver at either end of the data link do not always operate in exact synchronism with the data link, it is necessary to provide a pair of data synchronizing buffers, one between the data sender and the data link, and one between the data receiver and the data link.
IBM Technical Disclosure Bulletin article "Asynchronous Multi-Clock Bidirectional Buffer Control" by Brent et al (Vol. 24, No. 8, January 1982) page 4404, discusses a system which serves to synchronize transfers bidirectionally between two relatively asynchronous systems having different width data transfer interfaces.
U.S. Pat. No. 3,134,962 issued May 26, 1964 to Froehlich for "Serial Buffer", discloses a serial buffer which provides for the transmission of binary, digital data signals in serial form. The disclosed apparatus provides buffering means for matching an unsynchronized source to a synchronized transmission system, namely telephone lines operated at a fixed standard bit rate between transmitting and receiving stations.
U.S. Pat. No. 4,071,887 issued Jan. 31, 1978 to Daly et al for "Synchronous Serial Data Adapter", discloses an integrated circuit synchronous data adapter providing a bidirectional interface for synchronous data interchange. The disclosed adapter includes internal control and interface logic including a first-in-first-out (FIFO) buffer memory for enabling simultaneous transmitting and receiving of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bidirectional data bus of a bus organized system such as a microprocessor system.
U.S. Pat. No. 4,395,756 issued July 26, 1983 for "Processor Implemented Communications Interface Having External Clock Actuated Disabling Control" to Daniels, discloses an automated mailing system having a peripheral controller interface establishing communication links with peripheral devices, and an incompatible systems interface interconnecting a serial communications bus of the system processor and the peripheral controller interface. A flip-flop is provided to disable the incompatible systems processor to accommodate timing constraints of the serial communications bus for receipt of data signals.
U.S. Pat. No. 4,410,942 issued Oct. 18, 1983 for "Synchronizing Buffered Peripheral Subsystems to Host Operations" by Milligan et al, discloses a peripheral device subsystem which enables its peripheral devices to operate asynchronously with respect to attached hosts through use of manage buffers, new multiple data transfer modes, control and error recovery operations.
U.S. Pat. No. 4,686,690 issued Aug. 11, 1987 for "Synchronous Data Receiver Circuit" to Sato, discloses a synchronous data receiver circuit which, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data of the receive data in a data buffer.
U.S. Pat. No. 4,748,588 issued May 31, 1988 to Norman et al for "Fast Data Synchronizer", discloses a circuit arrangement for synchronizing source data from a source system with a clock from a sync system. The data synchronizer functions as a first-in-first-out (FIFO) buffer. Read and write counters are provided to affect data transfer, and are implemented as ring counters or gray code counters. By utilizing ring counters or gray code counters, glitchless detection of counter states is achieved. A detection circuit compares the state of the read and writer counters to determine if data to be synchronized exists in the buffer, and if empty buffer positions are available for additional data.